[ARM] coprocessor CP15 - system control coprocessor

Purpose

Cortex-A8 Technical Reference Manual Revision: r3p2 3.1. About the system control coprocessor

The purpose of the system control coprocessor, CP15, is to control and provide status information for the functions implemented in the processor. The main functions of the system control coprocessor are:

• overall system control and configuration
• cache configuration and management
• Memory Management Unit (MMU) configuration and management
• preloading engine for L2 cache
• system performance monitoring.

Instruction

mcr{cond} p15, <opcode_1>, <rd>, <CRn>, <CRm>, <opcode_2>
mrc{cond} p15, <opcode_1>, <rd>, <CRn>, <CRm>, <opcode_2>

Following the order, CRn -> Op1 -> CRm -> Op2, to look up the entry of target register in manual.


Cortex-A15 MPCore Technical Reference Manual Revision: r3p2 4.2. Register summary

Table 4.1. Column headings definition for CP15 register summary tables

Column name	Description
CRn	Register number within the system control coprocessor
Op1	Opcode_1 value for the register
CRm	Operational register number within CRn
Op2	Opcode_2 value for the register
Name	Short form architectural, operation, or code name for the register
Reset	Reset value of register
Description	Cross-reference to register description

Catagory

http://processors.wiki.ti.com/index.php/Cortex-A8_Architecture

Function	CP15 Registers
System Configuration	c0
System Control	c1
Translation Base Control	c2
Domain Access Control	c3
Faults	c5/c6
Cache Operations	c7
TLB Operations	c8/c10
Performance Monitor	c9
L2 Control	c9
Pre-load Engine	c11
Interrupts	c12
Process ID	c13
Memory Arrays	c15

Example

Cortex-A15 MPCore Technical Reference Manual Revision: r3p2 4.2.2. c1 registers

Table 4.3. c1 register summary

Op1	CRm	Op2	Name	Reset	Description
0	c0	0	SCTLR	0x00C50078[a]	System Control Register
		1	ACTLR	0x00000000	Auxiliary Control Register
		2	CPACR	0x00000000[b]	Coprocessor Access Control Register

....

The mapping is c1 -> 0 -> c0 -> to access System Control Register.

mcr p15, 0, rX, c1, c0, 0  : write arm to coprocessor , rX -> {c1, 0, c0, 0}

mrc p15, 0, rX, c1, c0, 0  : read coprocessor to arm , {c1, 0, c0, 0} -> rX

[ARM] DMB, DSB, ISB

Definition

Home > ARM and Thumb Instructions > Miscellaneous instructions > DMB, DSB, and ISB

DMB

Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction. It does not affect the ordering of any other instructions executing on the processor.

DSB

Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:

• All explicit memory accesses before this instruction complete.
• All Cache, Branch predictor and TLB maintenance operations before this instruction complete.

ISB

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the ISB instruction are visible to the instructions fetched after the ISB.

In addition, the ISB instruction ensures that any branches that appear in program order after it are always written into the branch prediction logic with the context that is visible after the ISB instruction. This is required to ensure correct execution of the instruction stream.