Definition
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DMB
Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in program order before the
DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction. It does not affect the ordering of any other instructions executing on the processor.DSB
Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:
- All explicit memory accesses before this instruction complete.
- All Cache, Branch predictor and TLB maintenance operations before this instruction complete.
ISB
Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the ISB instruction are visible to the instructions fetched after the ISB.
In addition, the ISB instruction ensures that any branches that appear in program order after it are always written into the branch prediction logic with the context that is visible after the ISB instruction. This is required to ensure correct execution of the instruction stream.
ISB
ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the ISB instruction are visible to the instructions fetched after the ISB.ISB instruction ensures that any branches that appear in program order after it are always written into the branch prediction logic with the context that is visible after the ISB instruction. This is required to ensure correct execution of the instruction stream.Difference
DMB acts obviously on memory operation instructions and also ISB is on instruction operation and internal state changing, but DSB is still unclear for me. I cannot distinguish the meaning "execute" of "no instruction in program order after this instruction executes ... " is only for the execution stage or describes even a instruction is not sent into the pipeline.
These pages, DMB Vs DSB, Memory access ordering part 3 - memory access ordering in the ARM Architecture, describes more clearly. DMB is a subset of DSB. ISB blocks instructions with instruction prefetch pipeline flushing so it has to refetch instructions from cache or memory for next instructions after ISB. DSB blocks both memory and instructions without cleaning the instruction prefetch pipeline.
There are diagrams for example to depict the scope of these instructions.
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Situations
It is important to know when to use these instructions.
In what situations might I need to insert memory barrier instructions?
如何使用内存隔离指令(memory barrier instructions) (a translation in Chinese)
See Also
Cortex-A7 pipeline
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