終於可以用ubuntu 連 nx 了

因為公司的server 用nx (no machine) 架的，最近公司電腦(win)不能用，雖然以前就有需要用自己的電腦連nx，但沒有急迫性，所以不能連就一直放著，這幾天不行了。

查過很多資料後我還是不太懂為什麼ubuntu 不能夠一開機就把這些事情做完整。

版本是10.04，遇到的狀況是 /tmp下沒有 .X11-unix/ ，這應該是xwin 會自己建的，維護一些socket的東西。此外還需要ssh支援forwarding，才能把遠端的視窗顯示在本機，但我試的結果是nx 好像不認識 :0.0。

首先要把 /etc/ssh/sshd_config 的 X11Forwarding 設 yes，http://serverfault.com/questions/99147/karmic-koala-ubuntu-enable-remote-x-clients-through-tcp ，參考這篇，改寫 /etc/gdm/gdm.schemas，

  <key>security/DisallowTCP</key>
  <signature>b>/signature>
  <default>false>/default>

還有 /etc/X11/xinit/xserverrc 把 -nolisten tcp 拿掉，打 netstat -an |grep 6000 會發現有service 在監聽。

這樣改完之後/tmp下還是不會建 .X11-unix，非常奇怪，我後來是自己建 .X11-unix 然後重啟 gdm，他會在/tmp下建立 .X0-lock 並且連結到 .X11-unix/X0 ，要出現這樣子才算可以顯示遠端視窗，只要沒有X0-lock 都算不成功的。

第一份工作的心得

在design house做了三年的DV，才疏學淺，但希望能夠將DV學完整，並有所發揮。目前大概就摸了半顆ic的程度。心得也只是在公司看到的狀況，不代表整個園區，觀念也不一定正確

很感謝當初找我進來的主管還有罩我的學長，不然以我講話很直的狀況，應該會一直被打槍吧。

未來不是現在，看看有沒有軟體部門要收留我吧，感覺os和compiler、fw那裡還滿有趣的

[ARM] coprocessor CP15 - system control coprocessor

Purpose

Cortex-A8 Technical Reference Manual Revision: r3p2 3.1. About the system control coprocessor

The purpose of the system control coprocessor, CP15, is to control and provide status information for the functions implemented in the processor. The main functions of the system control coprocessor are:

• overall system control and configuration
• cache configuration and management
• Memory Management Unit (MMU) configuration and management
• preloading engine for L2 cache
• system performance monitoring.

Instruction

mcr{cond} p15, <opcode_1>, <rd>, <CRn>, <CRm>, <opcode_2>
mrc{cond} p15, <opcode_1>, <rd>, <CRn>, <CRm>, <opcode_2>

Following the order, CRn -> Op1 -> CRm -> Op2, to look up the entry of target register in manual.


Cortex-A15 MPCore Technical Reference Manual Revision: r3p2 4.2. Register summary

Table 4.1. Column headings definition for CP15 register summary tables

Column name	Description
CRn	Register number within the system control coprocessor
Op1	Opcode_1 value for the register
CRm	Operational register number within CRn
Op2	Opcode_2 value for the register
Name	Short form architectural, operation, or code name for the register
Reset	Reset value of register
Description	Cross-reference to register description

Catagory

http://processors.wiki.ti.com/index.php/Cortex-A8_Architecture

Function	CP15 Registers
System Configuration	c0
System Control	c1
Translation Base Control	c2
Domain Access Control	c3
Faults	c5/c6
Cache Operations	c7
TLB Operations	c8/c10
Performance Monitor	c9
L2 Control	c9
Pre-load Engine	c11
Interrupts	c12
Process ID	c13
Memory Arrays	c15

Example

Cortex-A15 MPCore Technical Reference Manual Revision: r3p2 4.2.2. c1 registers

Table 4.3. c1 register summary

Op1	CRm	Op2	Name	Reset	Description
0	c0	0	SCTLR	0x00C50078[a]	System Control Register
		1	ACTLR	0x00000000	Auxiliary Control Register
		2	CPACR	0x00000000[b]	Coprocessor Access Control Register

....

The mapping is c1 -> 0 -> c0 -> to access System Control Register.

mcr p15, 0, rX, c1, c0, 0  : write arm to coprocessor , rX -> {c1, 0, c0, 0}

mrc p15, 0, rX, c1, c0, 0  : read coprocessor to arm , {c1, 0, c0, 0} -> rX

Those Things about Memory Mapping ... / Memory Mapping 的那些事

I have just learned computer architecture but OS so never linked them at all. These days I finished tracing a sample bootcode and read the arm programming guide. A sentence caught my eye which means every process has its own memory mapping, there are many page tables on runtime. I was too stupid to think there was only one page table where one program occupied part of memory and the code followed the rules in the part of memory, instructions on the bottom, stack on the top... Another impact was that it could allocate new memory by updating the page tables. I never knew it.

Several days after that day, I continuously construct the imagination of the code arrangement in the memory mapping, how the OS deals with the page tables. I only know that one program must ask the OS to get more space.

[ARM] DMB, DSB, ISB

Definition

Home > ARM and Thumb Instructions > Miscellaneous instructions > DMB, DSB, and ISB

DMB

Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction. It does not affect the ordering of any other instructions executing on the processor.

DSB

Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:

• All explicit memory accesses before this instruction complete.
• All Cache, Branch predictor and TLB maintenance operations before this instruction complete.

ISB

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the ISB instruction are visible to the instructions fetched after the ISB.

In addition, the ISB instruction ensures that any branches that appear in program order after it are always written into the branch prediction logic with the context that is visible after the ISB instruction. This is required to ensure correct execution of the instruction stream.